SDA_STUCK_RECOVERY_ENABLE=Val_0x0, TX_CMD_BLOCK=Val_0x0, ABORT=Val_0x0, ENABLE=Val_0x0
Enable Register
| ENABLE | Controls whether the I2C is enabled. When I2C is disabled, the following occurs:
0 (Val_0x0): Disables I2C (Tx and Rx FIFOs are held in an erased state) 1 (Val_0x1): Enables I2C |
| ABORT | When set, the controller initiates the transfer abort. 0 (Val_0x0): ABORT operation not in progress 1 (Val_0x1): ABORT operation in progress |
| TX_CMD_BLOCK | In Master mode: To block the execution of master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (I2C_STATUS[TFE] set to 0x1) and master is in IDLE state (I2C_STATUS[MST_ACTIVITY] is set to 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. 0 (Val_0x0): Tx Command execution not blocked. The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. 1 (Val_0x1): Tx Command execution blocked. Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. |
| SDA_STUCK_RECOVERY_ENABLE | If SDA is stuck at low indicated through the TX_ABORT interrupt(I2C_TX_ABRT_SOURCE[TX_ABORT] bit), then this bit is used as a control knob to initiate the SDA recovery mechanism (that is, send at most 9 SCL clocks and STOP to release the SDA line) and then this bit gets auto clear. 0 (Val_0x0): Master disables the SDA stuck at low recovery mechanism 1 (Val_0x1): Master initates the SDA stuck at low recovery mechanism |